1. Technical Field of the Invention
This invention relates generally to the field of electronic circuits and more particularly to a chip area efficient apparatus and method for providing both single clocked multiplexed data flip flop (MUX DFF) and level sensitive scan design (LSSD) scan flush testing capabilities.
2. Background Art
A most challenging item in VLSI design today is testing and test coverage. The IBM LSSD test methodology provides the highest test coverage of VLSI circuits, 100% coverage being achievable, but the disadvantage is that functional operation of the circuits requires two accurate clocks. MUX DFF is commonly used in the industry, and only one clock is required for functional operation, but the disadvantage is that data cannot be flushed through the scan path for system reset or manufacturing testing. The LSSD DMIMIC latch requires only one clock input for functional operation and is LSSD compatible, but the circuit implementation takes additional chip area (more than 30%) and it is not compatible with the industry MUX DFF scan methodology.
Consequently, there is a need in the art for a circuit providing the full capabilities of both MUX DFF and LSSD scan methodologies while requiring only about 10% more area than an LSSD latch alone.
Referring to FIG. 1, an example of a Level Sensitive Scan Design (LSSD) shift register latch (SRL), or basic LSSD polarity hold latch 100, is illustrated. Storage cells such as latches or flipflops are typically connected into a serial shift (scan) register for loading and unloading test vectors. The LSSD scan method typically used by IBM uses level-sensitive latches paired together as L1 master latch 101 and L2 slave latch 102 for scan operations. Each latch 101, 102 has at least one data port 104, 106, respectively, consisting of a data input 110, 114, respectively, and a clock input 112, 116, respectively. When the clock 112 or 116 is active, data is loaded into the corresponding latch on lines 110, 114, respectively. L1 master latch 101 has at least one data port 118 which receives scan data 120 when its LSSD A clock 122 is active. L2 slave latch 102 has at least one data port 106 which receives data 114 from L1 latch 101 when its clock, LSSD B clock 116, is active.
In this example, L1 master latch 101 has two ports 104, 118. C clock 112 enables functional data 110 into L1 master latch 101, and A clock 122 enables I scan data 120 into L1 master latch 101. B clock 116 enables L2 slave latch 102 to capture the data in L1 master latch 101 at its output 114. The output of L2 slave latch appears at Q output line 124.
The advantage of this LSSD approach is that there is completely separate control of the master and slave latch clocking times so that unique clocking methods and scan flush testing can be used. The disadvantage is that functional operation requires that two accurate clocks, B clock 116 and C clock 112, be provided to latches 101, 102. This causes increased complexity, clock skew, and the need for clock splitter circuits (an example of which is described hereafter) to be added into the logic if only a single clock is provided at the input.
Referring to FIG. 2, a second type of storage cell 130, called a multiplexed data flipflop (mux DFF, which is a D flipflop) 130 with only one clock 132 input to its L1 master latch 136 and L2 slave latch 137, is commonly used in industry. Inverter 139 inverts clock 132 for input to L1 master latch 136, and the data input 134 to L1 master latch 136 comes from a multiplexer 138 which selects between I scan data 140 and D functional data 142. The output of flipflop 146 appears at Q output line 146 from L2 slave latch 137. The advantage of this mux DFF approach is that only a single clock 132 is required to the storage cells 136, 137. Disadvantages are that data cannot be flushed through the scan path 140, 134, 144, 146 (for system reset or manufacturing test) and data path lengths (both functional data path 142, 134, 144, 146 and scan path 140, 134, 144, 146) must be long enough to avoid timing problems due to clock skew. By clock skew is meant the difference in arrival time of the clock signal 132 at different latches or flops 136, 137.
Referring to FIG. 3, a basic LSSD DMIMIC latch 200 is shown. This alternative for LSSD latches partially solves the functional clock problem by putting a clock splitter inside each latch, the L1 master latch 201 and L2 slave latch 202. Along with A clock 204, B clock 206 and C clock 208, an E clock 210 is provided. E clock 210 is inverted and fed to AND 213 along with C clock 208, the output forming the clock input 216 for clocking functional data 214 and A clock 204 clocks in I scan data 212. B clock 206 is fed to AND gate 217 along with E clock 210, and its output 218 is fed to L2 slave latch 202 for clocking the output 220 of L1 master latch 201. The output of L2 slave latch 202 appears at Q line 224. During functional operation, A clock 204 is held low, and B clock 206 and C clock 208 are held high while E clock 210 is used as the functional clock. This approach has the advantage of eliminating the need for a clock splitter in the clock distribution network and maintaining the LSSD properties of latches 201, 202. However, this DMIMIC 200 suffers from a number of problems which make its use unattractive. The main problem is that the additional circuitry adds about 30% to the physical area required for the latch 200, while an external clock splitter adds only about 15%. Therefore, using DMIMIC latches 200 costs chip area. The second problem is that the DMIMIC 200 requires an extra input (E clock 210) in order to provide the mimic function. A third problem is that this type of latch is still not compatible with the industry MUX DFF scan methodology.
Consequently, it is an object of the invention to provide a circuit which provides the full capabilities of both MUX DFF and LSSD scan methodologies.
It is a further object of the invention to provide a circuit which provides such full capabilities of both MUX DFF and LSSD scan methodologies while requiring only about 10% more area than an LSSD latch alone.